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| INTEGRATED CIRCUITS DATA SHEET SAA7240 MPEG-2 Transport RISC processor Product specification File under Integrated Circuits, IC02 2001 Oct 22 Philips Semiconductors Product specification MPEG-2 Transport RISC processor CONTENTS 1 1.1 1.2 1.3 1.4 1.5 2 2.1 2.2 3 4 5 5.1 5.2 5.3 6 7 8 9 9.1 9.2 10 10.1 10.2 11 12 12.1 12.2 12.3 12.4 12.5 13 14 15 16 FEATURES General External interfaces CPU-related features MPEG-2 System Processor (MSP) features Compatibility with other devices GENERAL DESCRIPTION Limitation notes Integrated Conditional Access Module (ICAM(R)) licensing requirements ORDERING INFORMATION BLOCK DIAGRAMS PINNING INFORMATION Pinning Pin description Pin list in numerical order LIMITING VALUES HANDLING THERMAL CHARACTERISTICS DC CHARACTERISTICS Power saving in Sleep and Coma modes Maximum allowable load capacitance on output pins APPLICATION INFORMATION Application examples of the multi-master mode Memory configurations PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS SAA7240 2001 Oct 22 2 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 1 1.1 FEATURES General SAA7240 * Conditional access descrambling Digital Video Broadcasting (DVB) compliant, MULTI2 compliant and ICAM(R) (1) compliant * Targeted to BSkyB 3.00 and Canal+ basic box 3.02 and web box 1.01 applications * Stream demultiplexing: Transport Stream (TS), Packetized Elementary Stream (PES), Program Stream (PS) and Proprietary data streams * Internal 32-bit MIPS RISC-based CPU, supporting MIPS16 instruction set and running at 81 MHz * Low-power Sleep modes supported across the chip * Support for external co-processor * 0.25 m technology * Power supply of 2.5 V for the core and 3.3 V for the peripherals, to be TTL level compatible * Comprehensive driver software and development tool support * Package: SQFP208. 1.2 External interfaces - Synchronous interface to communicate with the integrated MPEG Audio Video Graphics Decoder (AVGD) SAA7215 at 40.5 MHz - Large endian and small endian byte addressing - A multi-master mode (master and slave modes). * 2-channel Direct Memory Access (DMA) for fast block move to/from any memory location * Up to 12 chip selects available, some can be configured as general purpose ports * An IEEE 1284 interface (Centronics) with DMA engine supporting master and slave modes. Usable as a general purpose port * Two UART (RS232) data ports with DMA capabilities (at 187.5 kbit/s), including hardware flow control signals RXD, TXD, RTS and CTS for modem support * A Synchronous Serial Interface (SSI) to connect an off-chip modem analog front-end * An elementary UART with DMA capabilities, dedicated to front panel devices for instance * Two dedicated smart card reader interfaces (ISO 7816 compatible) with DMA capabilities. One interface is intended for the conditional access and is shared with the Integrated Conditional Access Module (ICAM) when ICAM is enabled; the second interface may be used for pay-per-view * Two I2C-bus master/slave transceivers with DMA capabilities, supporting the standard (100 kbit/s) and fast (400 kbit/s) I2C-bus modes * 32-bit general purpose port * Eight interrupt inputs * Parallel audio video interface to the MPEG AVGD decoder SAA7215 * One Pulse Width Modulated (PWM) output with 8-bit resolution * An Extended JTAG (EJTAG) interface for board test support. The SAA7240 supports the following external interfaces: * Versatile transport stream input/output at 13.5 Mbytes/s configurable in parallel or serial mode. Interfaces to IEEE 1394 devices (such as Philips PDI 1394 chip-set) in full-duplex mode and to external descramblers through a Common Interface (CI) device. The following interfaces are supported: - 3 parallel TS input/output ports - 2 parallel TS input/output ports and 3 serial TS ports - 1 parallel TS input/output port and 5 serial TS ports - 6 serial TS input/output ports. * A microcontroller extension bus, supporting: - 16-bit and 32-bit data buses - Up to 64 Mbytes addressing range - Synchronous Dynamic RAM (SDRAM) interface - Dynamic RAM interface - Read Only Memory (ROM) interface - Flash memory interface - Interface to various peripherals (1) Integrated Conditional Access Module (ICAM(R)) is an intellectual property of News Data System Corporation. 2001 Oct 22 3 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 1.3 CPU-related features SAA7240 - 4 TS/PES packet header filters (filter condition of 3 bytes, including PID value for TS packet header and specific filter condition for PES packet header) - 32 section filters based on a flexible number of filter conditions to retrieve PSI, SI, Private data and EPG, etc. Each section filter supports 48 filters conditions of 12 bytes; each filter condition can be negated or masked on a bit level - 7 ECM/EMM filters stored in on-chip RAM for ICAM implementation (ECM/EMM packets are stored in on-chip RAM) - Flexible 40 channel DMA-based storage of the 32 section sub-streams and four TS/PES data sub-streams and 4 TS/PES packet headers in external memory - System time base management with a double counter mechanism for clock control and discontinuity handling - Two Presentation Time Stamp (PTS)/Decoding Time Stamp (DTS) timers - A General Purpose/High Speed (GP/HS) filter, which can serve as an alternative input from IEEE 1394 devices, for example. The IEEE 1394 GP/HS mode supports packet insertion and has an internal SRAM for storing two packets. It can also output either scrambled or descrambled TS to IEEE 1394 devices. * A real time descrambler, supporting different descrambler algorithms and consisting of four modules: - A control word bank, containing 14 pairs (odd or even) of control words and a default control word - The DVB descrambler core, implementing the stream decipher and block decipher algorithms - The MULTI2 descrambler algorithm, implementing the CBC and OFB mode descrambling functions. In this mode, the maximum frequency is 9 Mbytes/s (72 Mbits/s) - The Integrated Conditional Access Module (ICAM), including an ISO 7816 compliant UART to interface the conditional access smart card. 1.5 Compatibility with other devices The SAA7240 contains an embedded RISC CPU, which incorporates the following features: * A 32-bit PR3930 core, running at 81 MHz * Support for large and small byte addressing modes; is ready for Windows(R) (1)CE and pSOS(R) (2) operating systems * 8-kbyte 2-way set of associative instruction cache * 4-kbyte 4-way set of associative data cache * A programmable low-power mode, including wake-up on interrupt * A Memory Management Unit (MMU) with 32 odd/even entries and variable page sizes * Multiply/accumulate/divide unit with fast multiply/accumulate for 16-bit and 32-bit operands * Two fully independent 24-bit timers and one 24-bit timer, including watchdog facilities * A real-time clock unit (active in Sleep mode) * Built-in software debug support unit as part of extended JTAG debug interface * On-chip SRAM of 4 kbytes for storing code that needs fast execution. 1.4 MPEG-2 System Processor (MSP) features * A flexible re-router to support many combinations of the transport stream input/output interfaces: - Connection to serial or parallel Common Interface IC - Connection to serial or parallel 1394 IC in full-duplex mode - Static dual front-end handling of channel decoders - A maximum frequency of up to 13.5 Mbytes/s in parallel mode and up to 81 Mbits/s in serial mode. * A demultiplexer scheme, which is fully compliant with Canal+ and BSkyB specifications: - Hardware-based parsing of transport, program and proprietary software data streams. The maximum input rate is 13.5 Mbytes/s in parallel mode and 81 Mbits/s in serial mode - Up to 40, 13-bit Packet Identifier (PID) filters applied on the PID value. 32 PID filters can be dedicated to filter packets containing sections; four PID filters to filter transport packets header; four PID filters to parse audio, video, teletext and subtitle data (1) Windows is a registered trademark of Microsoft Corporation (2) pSOS is a registered trademark of Wind River Systems, Inc. The SAA7240 seamlessly interfaces to the integrated MPEG AVGD decoder SAA7215HS. It is also backward compatible with the other devices of the family. The following modes/combinations are supported: * SAA7240 with SAA7215HS seamless * Pinning compatibility with the SAA7219HS. 2001 Oct 22 4 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 2 GENERAL DESCRIPTION SAA7240 low-power Sleep modes, which independently control the activity of each functional block and can sustain set-top box standby functionality, thus eliminating the need for a separate front-panel controller. The SAA7240 requires a supply voltage of 3.3 V for the I/O pads and a supply voltage of 2.5 V for the core. 2.1 Limitation notes The SAA7240 is a transport MPEG-2 source decoder designed for application in set-top boxes in a Digital Video Broadcast (DVB) environment. It is targeted to BSkyB 3.00 and Canal+ basic box and web box applications. The device is part of a comprehensive source decoding kit that contains all the hardware and software required to receive and decode MPEG-2 transport streams, including descrambling and demultiplexing. In addition, it includes a PR3930 core, which is a 32-bit MIPS RISC-based CPU core supporting the MIPS16 instruction set (to reduce memory requirements) and several peripheral interfaces such as UARTs, I2C-bus units, an IEC 1883, and an IEEE 1284 (Centronics) interface. The SAA7240 is therefore capable of performing all controller tasks in digital television applications. Furthermore, the SAA7240 complies with DVB, ICAM and MULTI2 descrambler standards. The SAA7240 receives transport streams through a versatile stream input interface capable of handling both byte-parallel and bit-serial streams, in various formats, supporting data streams up to and including 13.5 Mbytes/s in parallel mode and 81 Mbits/s in serial mode. The data stream is first applied to an on-chip descrambler with a DVB descrambling algorithm, on the basis of 14 control word pairs stored in an on-chip RAM. Demultiplexing is subsequently applied to the data stream, to separate up to 40 individual data streams. The demultiplexer section includes clock recovery and timebase management. Program Specific Information (PSI), Service Information (SI), Conditional Access (CA) messages and private data are selected and stored in external memory, for subsequent off-line processing by the internal PR3930 CPU core. To support advanced board testing facilities, the SAA7240 includes Boundary Scan Test (BST) hardware, according to the JTAG standard. The device features flexible 3 ORDERING INFORMATION Although the most advanced techniques and sophisticated tools are used during the design and validation phases, some design limitations giving some restrictions for specific applications might be discovered during the characterization of the SAA7240 and during its life time. If such an eventuality occurs, a limitation note will be issued, describing the deviation against the specification and the advised work-around if any. This limitation note, also sometimes called `anomaly sheet' or `bug list', is given to customers when they are in the initial design-in phase. Once the design-in is in production phase, customers are informed about any new limitation if the severity is estimated to be high. Please contact your nearest Philips Semiconductor sales office for more information. 2.2 Integrated Conditional Access Module (ICAM(R)) licensing requirements Companies planning to use ICAM(R) implementation in any final product must obtain a license from News Data System Corporation before designing such products. Additional per-chip royalties may be required and are to be paid by the purchaser to News Data System Corporation. For information on the Integrated Conditional Access Module features, a non-disclosure agreement must be signed with Philips Semiconductors to get the ICAM(R) specification. Please contact your nearest Philips Semiconductor sales office for more information. PACKAGE TYPE NUMBER NAME SAA7240 SQFP208 DESCRIPTION plastic shrink quad flat package, 208 leads (lead length 1.3 mm); body 28 x 28 x 34 mm; high stand-off height VERSION SOT316-1 2001 Oct 22 5 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ull pagewidth 2001 Oct 22 CPU section MIPS PR3930 CORE DATA CACHE INSTRUCTION CACHE TIMER 1 TIMER 2 TIMER 3 (WATCHDOG) DSU EJTAG MMU 4 Philips Semiconductors MPEG-2 Transport RISC processor BLOCK DIAGRAMS GPDATA PKTDATA GPD PWM MSP section(1) INPUT/OUTPUT ROUTER PWM DEMUX AND DESCRAMBLERS AUDIO AND VIDEO INTERFACE AV PES interface BUFFER POOL CONTROLLER RESETN M CLK 6 SAA7240 PI-bus S PI-BUS CTRL S EXTENSION BUS CONTROLLER AND DMA M CARD READER 0 1 M UART SSI 201 M S PIO INTERFACE M I2C-bus 0 1 M IEEE 1284 S RTC 32 kHz S INTERRUPT CONTROLLER S 4-KBYTE SRAM JTAG Peripheral section FCE811 EJTAG interface extension bus smart card interface SSI UART interface interface PIO interface I2C-bus IEEE 1284 interface interface Product specification M = master peripheral with embedded DMA channel S = slave peripheral (1) The MSP section is shown in more detail in Fig.2. SAA7240 Fig.1 Block diagram. Philips Semiconductors Product specification MPEG-2 Transport RISC processor SAA7240 handbook, full pagewidth TO / FROM SERIAL OR PARALLEL PORTS PKTDATA GPDATA GPD PWM INPUT / OUTPUT ROUTER INTERRUPT HANDLER INPUT INTERFACE PWM BIST CONTROLLERS PID FILTER DVB DESCRAMBLER MULTI2 DESCRAMBLER GP/HS PCR/SCR AV INTERFACE AV PES interface MPEG bus smart card interface CA/UART MODULE TS-PES PACKET FILTER 4 TS-PES HEADER FILTER 4 PI INTERFACE CONTROL & STATUS REGISTERS ECM/EMM FILTER RAM SECTION FILTER 32 BUFFER POOL CONTROLLER WITH 40 DMA CHANNELS PI-bus FCE824 Fig.2 MSP block diagram. 2001 Oct 22 7 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 5 5.1 PINNING INFORMATION Pinning SAA7240 208 handbook, halfpage 157 1 156 SAA7240HS 52 105 53 104 FCE812 Fig.3 Pin configuration. 2001 Oct 22 8 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 5.2 Pin description 2001 Oct 22 9 Philips Semiconductors MPEG-2 Transport RISC processor Table 1 Interface signal descriptions SYMBOL PIN TYPE DESCRIPTION BUFFER TYPE RESET STATE Programmable input/output port PIO[0:7]/INT[0:7] PIO8 PIO9 PIO10/BPN PIO11/VPP PIO12/C8 PIO13/C4 PIO14/BRN PIO15/BGN PIO[16:31]/D[16:31] 105 to 112 113 114 116 117 118 119 120 121 20 to 11, 9 to 4, 2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O lines or interrupt inputs I/O line I/O line I/O line or bus pre-empt; this requires the bus owner to release the bus after the current transfer I/O line or VPP; control signal for the supply voltage (ICAM) I/O line or IO data for conditional access (ICAM) I/O line or IO data for conditional access (ICAM) I/O line or bus request input I/O line or bus grant output I/O lines or upper data bus in 32-bit configuration bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 8 mA output drive; open-drain; bidirectional; 8 mA output drive; open-drain bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 3-state output; 2 mA output drive Z Z Z Z Z Z Z Z Z Z Extension bus interface D[0:15] A[0:21] A[22:25](1) RAS0N RAS1N/DCS1N LCASN/LBA#/SIZE0 49 48 46 41 to 28, 25 to 21 63 to 90 I/O O n.a. O O O lower 16-bit data bus address bus address bus extension shared with the IEEE 1284 interface row access strobe for DRAM and SDRAM bank 0 row access strobe for DRAM and SDRAM bank 1 or SDRAM chip select bank 1 column access strobe lower byte bidirectional; CMOS input; Z 3-state output; 2 mA output drive 3-state output; 2 mA output drive n.a. 3-state output; 2 mA output drive 3-state output; 2 mA output drive 3-state output; 2 mA output drive LOW n.a. Product specification SAA7240 HIGH HIGH HIGH This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Oct 22 10 Philips Semiconductors SYMBOL MLCASN/BAA#/SIZE1 MUCASN/SIZE2 UCASN WEN DCS0N CS[0:8]N CS[10:9]N(1) OEN/TSN DTACK CLK UART 0 interface TXD0 RXD0 RTSN0 CTSN0 TXD1/V34_TXD(2) RXD1/V34_RXD(2) RTSN1/V34_FS(2) CTSN1/V34_CLK(2) MCLK UART 2 interface Product specification TXD2 RXD2 136 135 O I UART 2 transmit data line UART 2 receive data line 2 mA output drive CMOS input HIGH 142 141 143 144 O I O I UART 0 transmit data line UART 0 receive data line UART 0 request to send UART 0 clear to send 2 mA output drive CMOS input 2 mA output drive CMOS input HIGH Z HIGH Z 58 59 91 45 44 42 62 47 56 to 50, 60, 61 PIN TYPE O O O O O O n.a. O I O DESCRIPTION column access strobe mid lower byte column access strobe mid upper byte column access strobe upper byte write enable chip select for SDRAM bank 0 chip select chip select extension shared with the IEEE 1284 interface output enable or Transfer Start indication data termination acknowledge 40.5 MHz clock BUFFER TYPE 3-state output; 2 mA output drive 3-state output; 2 mA output drive 3-state output; 2 mA output drive 3-state output; 2 mA output drive 3-state output; 2 mA output drive 3-state output; 2 mA output drive n.a. 3-state output; 2 mA output drive CMOS input 2 mA output drive RESET STATE HIGH HIGH HIGH HIGH HIGH HIGH n.a. HIGH Z T MPEG-2 Transport RISC processor UART 1 and SSI interface 138 137 139 140 146 O I I/O I O transmit data line or transmit serial data to the CODEC receive data line or receive serial data from CODEC request to send (output) or Frame synchronization reference from CODEC (input) clear to send or serial input clock from CODEC (up to 3.375 MHz) master clock to the CODEC (up to 36.864 MHz) 2 mA output drive CMOS input bidirectional; CMOS input; 2 mA output drive CMOS input 2 mA output drive HIGH Z HIGH Z T SAA7240 Z This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Oct 22 11 Philips Semiconductors SYMBOL I2C-bus 0 interface SDA0 SCL0 I2C-bus 1 interface SDA1 SCL1 Smart card 0 interface SC_I/O0 CLK_CARD0 CMDVCCN0 RSTIN0 OFFN0 Smart card 1 interface SC_I/O1 CLK_CARD1 CMDVCCN1 RSTIN1 OFFN1 126 122 123 124 125 I/O O O O I I/O line clock to the card command of the card power supply reset of the card card presence detection bidirectional; CMOS input; open-drain; 8 mA output drive 2 mA output drive 2 mA output drive 2 mA output drive CMOS input Z LOW HIGH HIGH Z 134 128 129 132 133 I/O O O O I I/O line clock to the card command of the card power supply reset of the card card presence detection bidirectional; CMOS input; open-drain; 8 mA output drive 2 mA output drive 2 mA output drive 2 mA output drive CMOS input Z LOW HIGH HIGH Z 148 147 I/O I/O data line clock line bidirectional; CMOS input; open-drain; 8 mA output drive bidirectional; CMOS input; open-drain; 8 mA output drive Z Z 150 149 I/O I/O data line clock line bidirectional; CMOS input; open-drain; 8 mA output drive bidirectional; CMOS input; open-drain; 8 mA output drive Z Z PIN TYPE DESCRIPTION BUFFER TYPE RESET STATE MPEG-2 Transport RISC processor Parallel or serial transport input interface from the front-end PKTDATA[0:7] PKTSTROBE PKTVALID PKTSYNC 164 to 157 154 156 155 I I/O I I 8-bit primary TS data input byte strobe or bit strobe data valid or bit stream word select packet synchronization CMOS input bidirectional; CMOS input; 2 mA output drive CMOS input Z Z Z Z Product specification SAA7240 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Oct 22 12 AVD3/STRAP3 AVD4/BIG AVD5/BOOTCS0 AVD6/BOOTW1 AVD7/BOOTW0 A_STROBE V_STROBE AV_ERROR 100 99 98 97 96 94 93 95 I/O I/O I/O I/O I/O O O O Philips Semiconductors SYMBOL PIN TYPE DESCRIPTION BUFFER TYPE RESET STATE MPEG-2 Transport RISC processor GP/HS interface (1 parallel port or 2 serial ports) GPDATA[0:7] GPSYNC GPVALID GPSTROBE Audio/video interface AVD0/STRAP0 AVD1/STRAP1 AVD2/STRAP2 103 102 101 I/O I/O I/O MPEG audio/video data stream output port 0; latched in PIO_STRAP register during reset MPEG audio/video data stream output port 1; latched in PIO_STRAP register during reset MPEG audio/video data stream output port 2; latched in PIO_STRAP register during reset MPEG audio/video data stream output port 3; latched in PIO_STRAP register during reset MPEG audio/video data stream output port 4; latched in PIO_STRAP register during reset MPEG audio/video data stream output port 5; latched in PIO_STRAP register during reset MPEG audio/video stream data output port 6; latched in PIO_STRAP register during reset MPEG audio/video stream data output port 7; latched in PIO_STRAP register during reset audio data strobe in the AVD stream video data strobe in the AVD stream flag for bit stream error (active HIGH) bidirectional; CMOS input; Z 3-state output; 2 mA output drive bidirectional; CMOS input; Z 3-state output; 2 mA output drive bidirectional; CMOS input; Z 3-state output; 2 mA output drive bidirectional; CMOS input; Z 3-state output; 2 mA output drive bidirectional; CMOS input; Z 3-state output; 2 mA output drive bidirectional; CMOS input; Z 3-state output; 2 mA output drive bidirectional; CMOS input; Z 3-state output; 2 mA output drive bidirectional; CMOS input; Z 3-state output; 2 mA output drive 2 mA output drive 2 mA output drive 2 mA output drive LOW LOW LOW 174 to 166 176 175 177 I/O I/O I/O I/O GP/HS data bus GP/HS synchronization GP/HS valid GP/HS strobe bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive Z Z Z Z Product specification SAA7240 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Oct 22 13 Philips Semiconductors SYMBOL PIN TYPE DESCRIPTION BUFFER TYPE RESET STATE MPEG-2 Transport RISC processor IEEE 1284 or transport stream interface GPD0/TS_DAT0 GPD1/TS_SYN0 GPD2/TS_VAL0 GPD3/TS_CK0 GPD4/TS_VAL1 GPD5/TS_SYN1 GPD6/TS_DAT1 GPD7/TS_CK1 NSELECTIN/TS_DAT2 NINIT/TS_SYN2 NSTROBE/TS_VAL2 190 191 192 193 194 195 196 197 199 200 201 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O parallel data bus or data for serial TSS2_in interface parallel data bus or sync for serial TSS2_in interface bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive Z Z Z Z Z Z Z Z Z Z Z parallel data bus or data valid for serial TSS2_in interface bidirectional; CMOS input; 2 mA output drive parallel data bus or clock for serial TSS2_in interface parallel data bus or data valid for serial CI_out interface parallel data bus or sync for serial CI_out interface parallel data bus or data for serial CI_out interface parallel data bus or clock for serial CI_out interface host to peripheral select line or data for serial CI_in interface host to peripheral control line or sync for serial CI_in interface host to peripheral strobe line or data valid for serial CI_in interface peripheral acknowledge line or clock for serial CI_in interface or chip select peripheral busy line or chip select peripheral error or address line peripheral on-line or address line peripheral error line or address line bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive bidirectional; CMOS input; 2 mA output drive NACK/CS10N/TS_CK2 202 BUSY/CS9N PERROR/A25 SELECT/A24 NAUTOF/A23 203 204 205 206 bidirectional; CMOS input; Z 3-state output; 2 mA output drive bidirectional; CMOS input; Z 3-state output; 2 mA output drive bidirectional; CMOS input; Z 3-state output; 2 mA output drive bidirectional; CMOS input; Z 3-state output; 2 mA output drive bidirectional; CMOS input; Z 3-state output; 2 mA output drive Product specification SAA7240 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Oct 22 14 Philips Semiconductors SYMBOL NFAULT/A22 DIR1284 PWM interface PWM0 System interface RESETN 1 I/O general system reset; active LOW; the pad is asserted bidirectional; CMOS input; LOW (if enabled) when the internal watch dog time-out is 4 mA output drive open drain; detected 13.5 MHz crystal input 13.5 MHz crystal output or external clock input oscillator input oscillator output LOW 165 O PWM output for VCXO control open-drain; 8 mA output drive LOW 207 208 PIN TYPE I/O O DESCRIPTION host to peripheral control line or address line direction control of the external buffers BUFFER TYPE RESET STATE MPEG-2 Transport RISC processor bidirectional; CMOS input; Z 3-state output; 2 mA output drive 2 mA output drive LOW XTAL1 XTAL2 JTAG and test interface TDO TDI TMS TRST TCK EJTAG interface DSU_CLK 153 152 I I/O T T 178 179 180 181 184 O I I I I test data output/target PC output test data input/debug interrupt test mode select test reset test clock 2 mA output drive CMOS input CMOS input CMOS input CMOS input Z Z Z Z Z 185 O DSU clock is equivalent to the processor clock; used to capture address and data from pin TDO when PC trace mode is on; is 3-stated when bit 0 or 15 of the JTAG_Control_Register is LOW or logic 0 CPU status (debug mode, pipeline stall and occurrence of exception) 2 mA output drive Z PCST[0:2] 186 to 189 O 2 mA output drive Z Product specification SAA7240 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Oct 22 15 Philips Semiconductors SYMBOL Power supplies VDDA VDDC VDDP 151 27, 79, 130, 182 3, 17, 31, 43, 66, 80, 92, 115, 145, 187 26, 78, 131, 183 10, 23, 37, 57, 72, 86, 104, 127, 170, 190 S S S 2.5 V analog supply voltage for the PLL and oscillator 2.5 V supply voltage for the core 3.3 V supply voltage for interface I/O pads n.a. n.a. n.a. PIN TYPE DESCRIPTION BUFFER TYPE RESET STATE MPEG-2 Transport RISC processor VSSC VSSP S S ground for the core ground for the interface pads n.a. n.a. Notes 1. These signals are internal. 2. Shared with UART 1 and SSI. Product specification SAA7240 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 5.3 Pin list in numerical order Numbered list of SAA7240 pins PIN 1 2 3, 17, 31, 43, 66, 80, 92, 115, 145, 187 4 5 6 7 8 9 RESETN PIO31/D31 VDDP PIO30/D30 PIO29/D29 PIO28/D28 PIO27/D27 PIO26/D26 PIO25/D25 NAME 42 44 45 46 47 48 49 50 51 52 53 54 55 56 58 59 60 61 62 63 64 65 67 68 69 70 71 73 74 75 76 77 81 82 83 84 85 87 88 89 90 16 SAA7240 PIN UCASN NAME MUCASN/SIZE2 MLCASN/BAA#/SIZE1 LCASN/LBA#/SIZE0 DCS0N RAS1N/DCS1N RAS0N CS6N CS5N CS4N CS3N CS2N CS1N CS0N OEN/TSN DTACK CS7N CS8N WEN A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 Table 2 10, 23, 37, 57, 72, 86, 104, VSSP 127, 170, 198 11 12 13 14 15 16 18 19 20 21 22 24 25 26, 78, 131, 183 27, 79, 130, 182 28 29 30 32 33 34 35 36 38 39 40 41 2001 Oct 22 PIO24/D24 PIO23/D23 PIO22/D22 PIO21/D21 PIO20/D20 PIO19/D19 PIO18/D18 PIO17/D17 PIO16/D16 D15 D14 D13 D12 VSSC VDDC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Philips Semiconductors Product specification MPEG-2 Transport RISC processor SAA7240 PIN 91 93 94 95 96 97 98 99 100 101 102 103 105 106 107 108 109 110 111 112 113 114 116 117 118 119 120 121 122 123 124 125 126 128 129 132 133 134 135 136 137 2001 Oct 22 CLK NAME 138 139 140 141 142 143 144 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 171 172 173 174 175 176 177 178 179 180 17 V_STROBE A_STROBE AV_ERROR AVD7/BOOTW0 AVD6/BOOTW1 AVD5/BOOTCS0 AVD4/BIG AVD3/STRAP3 AVD2/STRAP2 AVD1/STRAP1 AVD0/STRAP0 PIO0/INT0 PIO1/INT1 PIO2/INT2 PIO3/INT3 PIO4/INT4 PIO5/INT5 PIO6/INT6 PIO7/INT7 PIO8 PIO9 PIO10/BPN PIO11/VPP PIO12/C8 PIO13/C4 PIO14/BRN PIO15/BGN CLK_CARD1 CMDVCCN1 RSTIN1 OFFN1 SC_I/O1 CLK_CARD0 CMDVCCN0 RSTIN0 OFFN0 SC_I/O0 RXD2 TXD2 RXD1/V34_RXD PIN NAME TXD1/V34_TXD RTSN1/V34_FS CTSN1/V34_CLK RXD0 TXD0 RTSN0 CTSN0 MCLK SCL1 SDA1 SCL0 SDA0 VDDA XTAL2 XTAL1 PKTSTROBE PKTSYNC PKTVALID PKTDATA7 PKTDATA6 PKTDATA5 PKTDATA4 PKTDATA3 PKTDATA2 PKTDATA1 PKTDATA0 PWM0 GPDATA7 GPDATA6 GPDATA5 GPDATA4 GPDATA3 GPDATA2 GPDATA1 GPDATA0 GPVALID GPSYNC GPSTROBE TDO TDI TMS Philips Semiconductors Product specification MPEG-2 Transport RISC processor SAA7240 PIN 181 184 185 186 188 189 190 191 192 193 194 195 TRST TCK NAME 196 197 199 200 201 202 203 204 205 206 207 208 PIN NAME GPD6/TS_DAT1 GPD7/TS_CK1 NSELECTIN/TS_DAT2 NINIT/TS_SYN2 NSTROBE/TS_VAL2 NACK/CS10N/TS_CK2 BUSY/CS9N PERROR/A25 SELECT/A24 NAUTOF/A23 NFAULT/A22 DIR1284 DSU_CLK PCST0 PCST1 PCST2 GPD0/TS_DAT0 GPD1/TS_SYN0 GPD2/TS_VAL0 GPD3/TS_CK0 GPD4/TS_VAL1 GPD5/TS_SYN1 2001 Oct 22 18 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 6 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDP VI Ptot IDDC IDDP Tstg Tamb Tj Notes 1. System designers should be aware that: PARAMETER supply voltage for the I/O buffers input voltage on any pin with respect to ground (VSS) core supply current supply current for the I/O buffers storage temperature ambient temperature junction temperature MIN. SAA7240 MAX. UNIT V V -0.5 4.0 -0.5 3.0 VDDC, VDDA supply voltages for the core, PLL and oscillator -0.5 VDD + 0.5 V Ptot(max)(1) W 500(2) 330(3) 150 70 125 mA mA C C C - - -55 0 - total power dissipation (based on package transfer, not IC power consumption) - a) The IC junction temperature (Tj) is greatly influenced by the environment and the Printed-Circuit Board (PCB) layout thermal behaviour. Total allowable power Ptot in the customer application depends on its thermal characteristics; thermal resistance from junction to air; (Rth(j-a), refer to Chapter 8) and ambient temperature Tamb. Ptot(max) = (Tj(max) - Tamb)/Rth(j-a) = PINT + PI/O. PINT represents the internal device power (core and PLL). PI/O is the power dissipation in the input and output buffers. PINT depends on the user application and is limited by the maximum drive capability of the output buffers. b) Table 3 gives some examples of theoretical maximum power dissipation supported by the package; the designer has to check that there is no IDDP maximum current violation. 2. This value represents the maximum current that the power track can carry without excessive voltage drop in the internal chip. This value does not reflect the maximum current consumption of the core, which is far below this value. 3. This theoretical maximum value which should never be exceeded is determined when all output buffers are driving their specified maximum static drive current. In a standard application, this worst case never occurs because the output loads are mainly line capacitance and not resistive loads. 7 HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling CMOS integrated circuits. 8 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Note 1. When the device is soldered onto a PCB, the intrinsic thermal resistance of the package is improved. The Rth(j-a) value depends on the PCB type; some typical values are given below: a) For a standard PCB; Rth(j-a) = 32 C/W. b) For a 4-layer PCB; Rth(j-a) = 28 C/W. c) For a 4-layer PCB with thermal dissipation layer; Rth(j-a) = 24 C/W. PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 35(1) UNIT C/W 2001 Oct 22 19 Philips Semiconductors Product specification MPEG-2 Transport RISC processor Table 3 Theoretical package maximum power dissipation Ptot(max) at Tamb = 70 C 1.57 W 1.72 W 1.96 W 2.29 W Ptot at Tamb = 50 C 2.14 W 2.34 W 2.67 W 3.26 W SAA7240 THERMAL COEFFICIENT (Rth(j-a)) 35 C/W 32 C/W 28 C/W 24 C/W Ptot at Tamb = 25 C 2.85 W 3.12 W 3.57 W 4.34 W 9 DC CHARACTERISTICS VDDP = 3.0 to 3.6 V; VDDC = 2.25 to 2.75 V; VDDA = 2.25 to 2.75 V; VSS = 0 V; Tamb = 0 to 70 C; all voltages with respect to VSS; unless otherwise specified. SYMBOL VDDP VDDC VDDA IDDP IDDC IDDA IDDC(coma) Inputs VIL VIH VIH(XTAL1) IIL IIZ IIZ(off) Outputs VOH VOL Ci Notes 1. Typical current measured on a test board running a set-top box-like application (bitstream decoding and a few on-chip peripherals activated). 2. The typical current in Sleep and Coma modes is given in Table 4. HIGH-level output voltage LOW-level output voltage input capacitance output drive current = IOH(max) output sink current = IOL(min) 2.4 - - - - - - 0.4 10 V V pF LOW-level input voltage HIGH-level input voltage (except XTAL1) HIGH-level input voltage (XTAL1) input leakage current 3-state input current 3-state (off-state) input current; SDA, SCL and SC_I/O VDD = 3.3 V; VSS < Vi < VDD Vi = 2.4 or 0.4 V VDD = Vi = 3.6 V - 2.0 2.0 -10 -10 -10 - - - +1 +1 +1 0.8 V VDDP + 0.5 V 2.5 +10 +10 +10 V mA mA mA PARAMETER supply voltage for the I/O buffers supply voltage for the core analog supply voltage for PLL and oscillator supply current for the interface I/O pads core supply current analog supply current VDDP = 3.3 V VDDC = 2.5 V VDDA = 2.5 V; fclk = 13.5 MHz CONDITIONS MIN. 3.0 2.25 2.25 - - - - - TYP. 3.3 2.5 2.5 30(1) MAX. 3.6 2.75 2.75 - UNIT V V V mA mA mA mA mA 220(2) - 2(2) (2) (2) - - - IDDC(sleep) core supply current in Sleep mode values are measured at VDD(max); fclk = 13.5 MHz core supply current in Coma mode 2001 Oct 22 20 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 9.1 Power saving in Sleep and Coma modes SAA7240 Table 4 shows an example of typical current savings when either the Sleep mode or Coma mode is set. The measurement is carried out on a test board running an application at room temperature with VDDC = 2.5 V. First, the total current consumption of the SAA7240 is measured with all peripherals enabled; this value is taken as a reference. Then, the Sleep and Coma modes of the peripherals and CPU are set one at a time to measure the power consumption and determine the relevant current saving. Table 4 Typical current consumption for Sleep and Coma modes TYPICAL IDDC CURRENT (mA) 220(1) 210 208 12 12 SAVINGS (mA) n.a. 10 12 208 208 MIPS CONFIGURATION REGISTER VALUE 0000H 0001H 0002H 0004H 7FFFH Note PERIPHERAL no shutdown; used for reference CPU core in Sleep mode and peripherals active CPU core in Coma mode and peripherals active peripheral section in Coma mode and CPU active everything down; including CPU 1. This is the measured value used to determine the power savings. 9.2 Maximum allowable load capacitance on output pins Table 5 shows the maximum load capacitances that are allowed on the output pins. These loads should not be exceeded. Table 5 Maximum output load capacitances OUTPUT PIN SDA0, SCL0, SDA1 and SCL1 D[15:0], A[21:0], LCASN, MLCASN, MUCASN, UCASN, WEN, OEN and PIO[31:16]/D[31:16] CLK, MCLK, DSU_CLK and PCST[2:0] PKTSTROBE, GPDATA[7:0], GPSYNC, GPVALID, GPSTROBE, GPD0/TS_DAT0, GPD1/TS_SYN0, GPD2/TS_VAL0, GPD3/TS_CK0, GPD4/TS_VAL1, GPD5/TS_SYN1, GPD6/TS_DAT1, GPD7/TS_CK1, NSELECTIN/TS_DAT2, NINIT/TS_SYN2, NSTROBE/TS_VAL2 and NACK/CS10N/TS_CK2 All other outputs MAXIMUM LOAD 400 100 25 20 UNIT pF pF pF pF 50 pF 2001 Oct 22 21 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 10 APPLICATION INFORMATION SAA7240 handbook, full pagewidth RF-in TDA8060 TDA5056 TUNER 2 SAA8044 (SDD) I2C-bus MPEG-2 BUFFERS IEEE1394 L + PHY IEEE 1284 RS232 IEEE 1394 FRONT PANEL CONTROL Telco interface smart cards VXX MODEM SAA7240 TDA8004 AV PES 16-Mbit SDRAM FLASH DRAM (OPTIONAL) SAA7215 16-Mbit SDRAM (OPTIONAL) CVBS/YC LR ADAC RGB SWITCHING SCART1 SCART2 SCART3 FCE815 Fig.4 Set-top box example. 2001 Oct 22 22 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 10.1 Application examples of the multi-master mode SAA7240 The SAA7240 supports a multi-master mode. The SAA7240 is always the bus arbiter of the External Bus Interface Unit (EBIU) bus. The possible configurations are depicted in Figs 5 and 6. handbook, full pagewidth 16-Mbit VIDEO 16-Mbit GRAPHICS AV PES BPN SAA7240 BGN BRN SAA7215 EBIU BUS GATEWAY ROM FLASH SDRAM PERIPHERAL CO-PROCESSOR FCE813 Fig.5 Multi-master mode; EBIU bus is shared with a co-processor. handbook, full pagewidth 16-Mbit VIDEO 16-Mbit GRAPHICS AV PES BPN SAA7240 BGN BRN SAA7215 EBIU BUS GATEWAY SAA7215 BUS ROM FLASH SDRAM PERIPHERAL CO-PROCESSOR FCE814 Fig.6 Multi-master mode; EBIU bus is split with a co-processor. 2001 Oct 22 23 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 10.2 Memory configurations SAA7240 Figures 7 and 8 show some examples of typical set-top box memory configurations. handbook, full pagewidth 16 DRAM/ SDRAM 8 PROM FLASH RESERVED SAA7240 16 16 SDRAM (MPEG) FCE816 SAA7215 Fig.7 Typical low-end memory configuration; data bus is 16 bits wide. handbook, full pagewidth 32 DRAM/ SDRAM 32 PROM FLASH-1 FLASH-2 SAA7240 16 16 SDRAM (MPEG) SAA7215 16 SDRAM GRAPHICS FCE817 Fig.8 Typical high-end configuration; data bus is 32 bits wide. 2001 Oct 22 24 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 11 PACKAGE OUTLINE SQFP208: plastic shrink quad flat package; 208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm; high stand-off height SAA7240 SOT316-1 c y X A 156 157 105 104 ZE e E HE A2 A1 (A 3) Lp L pin 1 index 208 53 52 A wM bp detail X 1 e bp D HD wM ZD B vM A vM B 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT316-1 REFERENCES IEC JEDEC MS-029 EIAJ EUROPEAN PROJECTION A max. 4.10 A1 0.50 0.25 A2 3.6 3.2 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.5 HD 30.9 30.3 HE 30.9 30.3 L 1.3 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.39 1.11 1.39 1.11 8 0o o ISSUE DATE 99-12-27 00-01-25 2001 Oct 22 25 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 12 SOLDERING 12.1 Introduction to soldering surface mount packages SAA7240 If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 12.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 12.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 12.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2001 Oct 22 26 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 12.5 Suitability of surface mount IC packages for wave and reflow soldering methods SAA7240 SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable 2001 Oct 22 27 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 13 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS SAA7240 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 14 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 15 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. ICs with MPEG-2 functionality Use of this product in any manner that complies with the MPEG-2 Standard is expressly prohibited without a license under applicable patents in the MPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C., 250 Steele Street, Suite 300, Denver, Colorado 80206. 2001 Oct 22 28 Philips Semiconductors Product specification MPEG-2 Transport RISC processor 16 PURCHASE OF PHILIPS I2C COMPONENTS SAA7240 Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2001 Oct 22 29 Philips Semiconductors Product specification MPEG-2 Transport RISC processor NOTES SAA7240 2001 Oct 22 30 Philips Semiconductors Product specification MPEG-2 Transport RISC processor NOTES SAA7240 2001 Oct 22 31 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2001 SCA73 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/01/pp32 Date of release: 2001 Oct 22 Document order number: 9397 750 07749 |
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